r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 358

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Interrupt Controller (INTC)
9.4
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip modules. Each interrupt has
a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set,
the interrupt is masked and interrupt requests are ignored.
9.4.1
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in
SR of the CPU is set to 1. In sleep mode, the interrupt is accepted even if the BL bit is set to 1.
A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input
from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in ICR0 is used to select
either rising or falling edge as the detection edge. When the NMIE bit in ICR0 is modified, the
NMI interrupt is not detected for a maximum of six bus clock cycles after the modification. If the
INTMU bit in CPUOPM is set to 1, the IMASK value in SR is automatically set to 15 by the
accepted NMI interrupt. If the INTMU bit in CPUOPM is set to 0, the IMASK value in SR is not
affected by the NMI interrupt exception handling.
9.4.2
IRQ interrupts are available when using the IRQ7/IRL7 to IRQ0/IRL0 pin for IRQn (n = 7 to 0)
independent interrupt inputs by setting the IRLM0 and IRLM1 bits to 1 in ICR0. The IRQnS1 and
IRQnS0 bits in ICR1 are used to select either rising edge, falling edge, low level, or high level
detection. A priority level can be set for each input by using the interrupt priority level setting
register (INTPRI).
When level detection is selected for IRQ interrupt requests, the IRQ interrupt pin input level
should be held until the CPU accepts the interrupt and starts interrupt handling. In level detection
mode, after an interrupt request is accepted, the interrupt request held in the detection circuit
should be cleared. For the specific clearing procedure, see section 9.7.3, To Clear IRQ and IRL
Interrupt Requests.
Note: In level detection mode, once an IRQ interrupt request has been detected, the INTC holds
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the interrupt request as the interrupt source in INTREQ even if the corresponding IRQ
interrupt pin level is changed to cancel the request before the CPU accepts the request.
The interrupt source will be held until the CPU accepts any other interrupt request (IRQ or
not) or the corresponding interrupt mask bit is set to 1. For details, see section 9.7, Usage
Notes.
Interrupt Sources
NMI Interrupt
IRQ Interrupts