r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 13

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

9.4
9.5
9.6
9.7
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10 Interrupt mask clear register 2 (INTMSKCLR2).................................................. 260
9.3.11 NMI Flag Control Register (NMIFCR) ................................................................ 263
9.3.12 User Interrupt Mask Level Register (USERIMASK) ........................................... 264
9.3.13 On-chip module Interrupt Priority Registers (INT2PRI0 to INT2PRI13) ............ 266
9.3.14 Interrupt Source Register 0 (Mask State is not affected) (INT2A0) ..................... 268
9.3.15 Interrupt Source Register 01 (Mask State is not affected) (INT2A01) ................. 269
9.3.16 Interrupt Source Register (Mask State is affected) (INT2A1) .............................. 272
9.3.17 Interrupt Source Register 11 (Mask State is affected) (INT2A11) ....................... 274
9.3.18 Interrupt Mask Register (INT2MSKR)................................................................. 276
9.3.19 Interrupt Mask Register 1 (INT2MSKR1)............................................................ 277
9.3.20 Interrupt Mask Clear Register (INT2MSKCR)..................................................... 279
9.3.21 Interrupt Mask Clear Register 1 (INT2MSKCR1)................................................ 281
9.3.22 On-chip Module Interrupt Source Registers (INT2B0 to INT2B7 and
9.3.23 GPIO Interrupt Set Register (
Interrupt Sources................................................................................................................ 292
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Operation ........................................................................................................................... 305
9.5.1
9.5.2
9.5.3
Interrupt Response Time.................................................................................................... 308
Usage Notes ....................................................................................................................... 309
9.7.1
9.7.2
9.7.3
Interrupt Source Register (INTREQ).................................................................... 250
Interrupt Mask Register 0 (INTMSK0) ................................................................ 251
Interrupt mask register 1 (INTMSK1) .................................................................. 253
Interrupt mask register 2 (INTMSK2) .................................................................. 254
Interrupt Mask Clear Register 0 (INTMSKCLR0) ............................................... 257
Interrupt mask clear register 1 (INTMSKCLR1).................................................. 259
INT2B9 to INT2B11) ........................................................................................... 283
NMI Interrupt........................................................................................................ 292
IRQ Interrupts ....................................................................................................... 292
IRL Interrupts ....................................................................................................... 293
On-chip Module Interrupts ................................................................................... 295
Interrupt Priority Level of On-chip Module Interrupts ......................................... 295
Interrupt Exception Handling and Priority............................................................ 296
Interrupt Sequence ................................................................................................ 305
Multiple Interrupts ................................................................................................ 307
Interrupt Masking by MAI Bit .............................................................................. 307
Example of Interrupt Handling Routine for Level-Encoded IRL and
Level-Sensed IRQ................................................................................................. 309
Notes on Setting IRQ7/IRL7 to IRQ0/IRL0 Pin Function.................................... 310
To Clear IRQ and IRL Interrupt Requests ............................................................ 310
INT2GPIC
) .............................................................. 289
Rev. 1.00 Oct. 01, 2007 Page xiii of lxvi