r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 438
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
- Current page: 438 of 2026
- Download datasheet (12Mb)
Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 372 of 1956
REJ09B0256-0100
Figure 11.10 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting)
(read)
(read)
WEn
(Write)
D31 to D0
(Write)
CLKOUT
A25 to A0
CSn
RDWR
D31 to D0
BS
Note:
RD
* When CSnBCR RDSPL is set to 1.
T
AS1
T
AS1
: Address Setup wait
CSnWCR RDS
: Address Setup wait
T
CSnWCR ADS
CLKOUT
AS1
(0 to 7)
(0 to 7)
T
T
S1
S1
CSnWCR WTS
T
CSnWCR RDS
: WE Setup wait
1
: RD Setup wait
(0 to 7)
(0 to 7)
T
S1
T
W
T
T
CSnWCR IW
w
CSnWCR IW
w
: Access wait
T
: Access wait
(0 to 25)
W
(0 to 25)
T
W
CLKOUT
T
W
T
T
T
2
H1
H1
, T
, T
CSnWCR WTH
SnWCR RDH
T
H2
H2
H1
(0 to 7)
(0 to 7)
: RD Hold wait
: WE Hold wait
*
T
T
AH1
AH1
T
CSnWCR ADH
: Address Hold wait
H2
CSnWCR AHS
: Address Hold wait
(0 to 7)
T
(0 to 7)
AH1
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