r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1295

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

29.4.7
(1)
Figure 29.9 shows an example of settings and operation for master mode transmission.
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the
No.
1
2
3
4
5
6
7
8
Transmission in Master Mode
TXE bit should be set to 1.
Transmit and Receive Procedures
Set the SCKE bit in SICTR to 1
Clear the TXE bit in SICTR to 0
Transmit SITDR from SIOF_TXD
synchronously with SIOF_SYNC
SICDAR, SITCR, and SIFCTR
Set SIMDR, SISCR, SITDAR,
Set the FSE and TXE bits
Start SIOF_SCK output
Figure 29.9 Example of Transmit Operation in Master Mode
Flow Chart
in SICTR to 1
TDREQ = 1?
Set SITDR
Transfer
ended?
Start
End
Yes
Yes
No
No
Set operating mode, serial clock,
slot positions for transmit data,
slot position for control data,
control data, and FIFO request
threshold value
Set operation start for baud rate
generator
Set the start for frame synchronous
signal output and enable transmission
Set transmit data
Set to disable transmission
SIOF Settings
Rev. 1.00 Oct. 01, 2007 Page 1229 of 1956
Section 29 Serial I/O with FIFO (SIOF)
Output serial clock
Output frame synchronous
signal and issue transmit
transfer request*
Transmit
End transmission
SIOF Operation
REJ09B0256-0100