r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 405

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
16
15
14
13 to 7
6 to 0
Bit Name
DMABST

HIZCNT

ASYNC[6:0]
Initial
Value
0
0
0
0
All 0
R/W
R/W
R
R/W
R
R/W
Description
DMAC Burst Mode Transfer Priority Setting
Specifies the priority of burst mode transfers by the
DMAC. When this bit is cleared to 0, the priority is as
follows: bus release, DMAC, CPU. When this bit is set
to 1, the bus release is not performed until the
completion of the DMAC burst transfer. This bit is
initialized at a power-on reset.
0: DMAC burst mode transfer priority setting off
1: DMAC burst mode transfer priority setting on
Reserved
This bit is always read as 0. The write value should
always be 0.
High Impedance (Hi-Z) Control
Specifies the state of signals WEn and RD/FRAME
during the software standby mode and the bus-released
state.
0: Signals of WEn and RD/FRAME are high-impedance
1: Signals of WEn and RD/FRAME are output during
Reserved
These bits are always read as 0. The write value should
always be 0.
Asynchronous Input
Enable asynchronous input to the corresponding pins.
0: Input signals to the corresponding pins are
1: Input signals to the corresponding pins are
ASYNC[6]: DREQ3
ASYNC[5]: DREQ2
ASYNC[4]: DREQ1
ASYNC[3]: DREQ0
ASYNC[2]: IOIS16
ASYNC[1]: BREQ
ASYNC[0]: RDY
during the bus-released state
the bus-released state
synchronized with CLKOUT
asynchronous to CLKOUT
Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 339 of 1956
REJ09B0256-0100