r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 873

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

ARSTR resets all blocks (E-MAC, TSU, and E-DMAC) in the GETHER. By writing 1 to the

ARST bit in this register, a software reset is issued to all blocks of the GETHER (for 256 cycles of

external bus clock Bck). The ARST bit is always read as 0. While a software reset is issued,

Initial value:

Software Reset Register (ARSTR)

These bits are always read as 0. The write value should

always be 0.

Software Reset

When 1 is written to this bit, a software reset is issued

to all blocks of the GETHER (for 256 cycles of external

bus clock Bck). Writing 0 does not affect this bit. This

bit is always read as 0. While a software reset is

issued, register access to all blocks of the GETHER is

prohibited. The following registers are not initialized by

a software reset.

TSU_ADRH0 to TSU_ADRH31, TSU_ADRL0 to

TSU_ADRL31, TXNLCR0, TXNLCR1, TXALCR0,

TXALCR1, RXNLCR0, RXNLCR1, RXALCR0,

RXALCR1, FWNLCR0, FWNLCR1, FWALCR0,

When relay operations from the E-MAC-1 to E-MAC-0

or from the E-MAC-0 to E-MAC-1 are enabled, a reset

must be issued using this bit. A software reset issued

by the SWRT and SWRR bits in EDMR does not reset

the transfer switching unit (TSU) performing data

transfer between the E-MAC-1 and E-MAC-0.

Section 23 Gigabit Ethernet Controller (GETHER)

Rev. 1.00 Oct. 01, 2007 Page 807 of 1956

REJ09B0256-0100