r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1258

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 29 Serial I/O with FIFO (SIOF)
29.3.1
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
Rev. 1.00 Oct. 01, 2007 Page 1192 of 1956
REJ09B0256-0100
Initial value:
Bit
15, 14
13
12
11 to 8
R/W:
BIt:
Mode Register (SIMDR)
Bit Name
TRMD[1:0]
SYNCAT
REDG
FL[3:0]
R/W
TRMD[1:0]
15
1
R/W
14
0
R/W
SYN
CAT
13
0
Initial
Value
10
0
0
0000
REDG
R/W
12
0
R/W
R/W
R/W
R/W
R/W
R/W
11
0
R/W
10
0
FL[3:0]
Description
Transfer Mode
Select transfer mode as shown in table 29.4.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
SIOF_SYNC Pin Valid Timing
Indicates the position of the SIOF_SYNC signal to be
output as a synchronization pulse.
0: At the start-bit data of frame
1: At the last-bit data of slot
Receive Data Sampling Edge
0: The SIOF_RXD signal is sampled at the falling edge
1: The SIOF_RXD signal is sampled at the rising edge
Note: The timing to transmit the SIOF_TXD signal is at
Frame Length
Specifies the flame length and transfer data format. For
details, refer to table 29.7.
R/W
of SIOF_SCK
of SIOF_SCK
0
9
R/W
the opposite edge of the timing that samples the
SIOF_RXD. This bit is valid only in master
mode.
8
0
TXDIZ
R/W
7
0
RCIM
R/W
6
0
R/W
SYN
CAC
5
0
R/W
SYN
CDL
4
0
—
R
3
0
—
R
2
0
—
R
1
0
—
R
0
0