r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 260

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Caches
7.2.3
QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled.
Rev. 1.00 Oct. 01, 2007 Page 194 of 1956
REJ09B0256-0100
Initial value:
Initial value:
Bit
31 to 5
4 to 2
1, 0
R/W:
R/W:
Bit:
Bit:
Queue Address Control Register 1 (QACR1)
Bit Name

AREA1

31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
Undefined R/W
All 0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R
26
10
R
R
0
0
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
When the MMU is disabled, these bits generate
physical address bits [28:26] for SQ1.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
R/W
20
R
0
4
AREA1
R/W
19
R
0
3
R/W
18
R
0
2
17
R
R
0
1
0
16
R
R
0
0
0