r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1276

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 29 Serial I/O with FIFO (SIOF)
Rev. 1.00 Oct. 01, 2007 Page 1210 of 1956
REJ09B0256-0100
Bit
10
9
8
7, 6
5
4
3
2
1
0
Bit Name
RCRDYE
RFFULE
RDREQE
SAERRE
FSERRE
TFOVFE
TFUDFE
RFUDFE
RFOVFE
Initial
Value
0
0
0
All 0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Receive FIFO Full Enable
Transmit FIFO Overflow Enable
Receive FIFO Overflow Enable
Description
Receive Control Data Ready Enable
0: Disables interrupts due to receive control data ready
1: Enables interrupts due to receive control data ready
0: Disables interrupts due to receive FIFO full
1: Enables interrupts due to receive FIFO full
Receive Data Transfer Request Enable
0: Disables interrupts due to receive data transfer
1: Enables interrupts due to receive data transfer
Reserved
These bits are always read as 0. The write value should
always be 0.
Slot Assign Error Enable
0: Disables interrupts due to slot assign error
1: Enables interrupts due to slot assign error
Frame Synchronization Error Enable
0: Disables interrupts due to frame synchronization
1: Enables interrupts due to frame synchronization error
0: Disables interrupts due to transmit FIFO overflow
1: Enables interrupts due to transmit FIFO overflow
Transmit FIFO Underflow Enable
0: Disables interrupts due to transmit FIFO underflow
1: Enables interrupts due to transmit FIFO underflow
Receive FIFO Underflow Enable
0: Disables interrupts due to receive FIFO underflow
1: Enables interrupts due to receive FIFO underflow
0: Disables interrupts due to receive FIFO overflow
1: Enables interrupts due to receive FIFO overflow
error
requests
requests

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