r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 643

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
27 to 25
24
23
22
21
Bit Name
RPT[2:0]
—
DO
—
DVMD
Initial
Value
000
0
0
0
0
R/W
R/W
R
R/W
R
R/W
Descriptions
DMA Setting Renewal Specify
These bits are enabled in CHCR0 to CHCR3.
000: Normal mode
001: Repeat mode
010: Repeat mode
011: Repeat mode
100: Reserved (setting prohibited)
101: Reload mode
110: Reload mode
111: Reload mode
Reserved
This bit is always read as 0. The write value should
always be 0.
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR0 to CHCR3.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
Reserved
This bit is always read as 0. The write value should
always be 0.
Division Transfer Mode Specification
Specifies the execution of the DMA transfer in 16-byte
units between the on-chip peripheral module STIF and
the external memory.
When the STIF is used, always write 1 to this bit. When
the STIF is not used, always write 0 to this bit.
SAR/DAR/TCR used as repeat area
DAR/TCR used as repeat area
SAR/TCR used as repeat mode
SAR/DAR/TCR used as reload area
DAR/TCR used as reload area
SAR/TCR used as reload area
Section 14 Direct Memory Access Controller (DMAC)
Rev. 1.00 Oct. 01, 2007 Page 577 of 1956
REJ09B0256-0100