r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 259

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

7.2.2
QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is disabled.
Bit
0
Initial value:
Initial value:
Bit
31 to 5
4 to 2
1, 0
R/W:
R/W:
Bit:
Bit:
Queue Address Control Register 0 (QACR0)
Bit Name
OCE
Bit Name

AREA0

31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
0
Initial
Value
All 0
Undefined R/W
All 0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R/W
R/W
R
R
26
10
R
R
0
0
Description
OC Enable Bit
Selects whether the OC is used. Note however when
address translation is performed, the OC cannot be
used unless the C bit in the page management
information is also 1.
0: OC not used
1: OC used
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
When the MMU is disabled, these bits generate
physical address bits [28:26] for SQ0.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 193 of 1956
22
R
R
0
6
0
21
R
R
0
5
0
R/W
20
R
0
4
AREA0
R/W
19
R
0
3
Section 7 Caches
REJ09B0256-0100
R/W
18
R
2
0
17
R
R
0
1
0
16
R
R
0
0
0