r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 530

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 13 PCI Controller (PCIC)

This status register is used to record status information for PCI bus related events. The definition

of each of the bits is given in the table below. A device may not need to implement all the bits,

depending on device functionality. For instance, since a device that acts as a target does not

inform a target abort, bit 11 does not need to be implemented. Reserved bits should be read-only

and return zero when the bits are read.

Reads from this register operates normally. Writes are slightly different in that bits can be cleared,

but not set. A one bit is cleared whenever the register is written to, and the write data in the

corresponding bit location is a 1. For instance, to clear bit 14 and not affect any other bits, write

the value of B'0100 0000 0000 0000 to the register.

Rev. 1.00 Oct. 01, 2007 Page 464 of 1956

REJ09B0256-0100

Initial value:

PCI Status Register (PCISTATUS)

Parity Error Detect Status

Indicates that a parity error has been detected in read

data when the PCIC is a master or in write data when

the PCIC is a target.

This bit must be set by the device whenever it detects

a parity error, even if parity error handling is disabled.

0: Device is not detecting parity error.

1: Device is detecting parity error.

System Error Output Status

Indicates that the PCIC has asserted the SERR

0: SERR has not been asserted

1: SERR has been asserted (the value retained until