r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 427

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

11.5.2
(1)
For area 0, external address bits A28 to A26 are 000.
The interfaces that can be set for this area are the SRAM, MPX, and burst ROM interfaces.
A bus width of 8, 16, or 32 bits is selectable with external pins MD4 and MD3 at a power-on reset.
For details, see section 11.3.2, Memory Bus Width.
When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used
as OE, and write control signals WE0 to WE3 are asserted.
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS0WCR can be selected.
When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable
with bits BW[2:0] in CS0BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
When the burst ROM interface is used, the number of transfer cycles for a burst cycle is selected
from a range of 2 to 9 according to the number of wait cycles.
The setup time and hold time (cycle number) of the address and CS0 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS0WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
(2)
For area 1, external address bits A28 to A26 are 001.
The interfaces that can be set for this area are the SRAM, MPX, burst ROM and byte-control
SRAM interfaces.
A bus width of 8, 16, or 32 bits is selectable with bits SZ[1:0] in CS1BCR. When the MPX
interface is used, a bus width of 32 bits should be selected through bits SZ[1:0] in CS1BCR. When
using the byte-control SRAM interface, select a bus width of 16 or 32 bits.
When area 1 is accessed, the CS1 signal is asserted. In the case where the SRAM interface is set,
the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
Area 0
Area 1
Areas
Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 361 of 1956
REJ09B0256-0100