r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1055

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.5.4
MII registers in the PHY-LSI are accessed via PIR in this LSI. PIR is used as a serial interface
conforming to the MII frame format specified in IEEE802.3u.
(1)
Figure 23.32 shows the format of an MII management frame. To access an MII register, a
management frame is implemented by the program in accordance with the procedures shown in
MII Register Access Procedure.
MII Management Frame Format
[Legend]
Accessing MII Registers
PRE:
ST:
OP:
PHYAD:
REGAD:
TA:
DATA:
IDLE:
Number of bits
Access Type
Read
Write
Item
32 consecutive 1s
Write of 01 indicating start of frame
Write of code indicating access type
Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI address.
Write of 000q if the register address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI register address.
Time for switching data transmission source on MII interface
(a) Write: 10 written
(b) Read: Bus release (notation: Z0) perdormed
16-bit data. Sequential write or read from MSB
(a) Write: 16-bit data write
(b) Read: 16-bit data read
Wait time until next MII management format input
(a) Write: Independent bus release (notation: X) performad
(d) Read: Bus already released in TA: control unnecessary
Figure 23.32 MII Management Frame Format
PRE
1..1
1..1
32
ST
01
01
2
OP
10
01
2
MII Management Frame
PHYAD
00001
00001
5
Section 23 Gigabit Ethernet Controller (GETHER)
REGAD
RRRRR
RRRRR
Rev. 1.00 Oct. 01, 2007 Page 989 of 1956
5
TA
Z0
10
2
DATA
D..D
D..D
16
REJ09B0256-0100
IDLE
X