r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 271

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

PURGE transaction: When the operand cache is enabled, the PURGE transaction checks the

operand cache and invalidates the hit entry. If the invalidated entry is dirty, the data is written back

to the external memory. If the transaction is not hit to the cache, it is no-operation.

FLUSH transaction: When the operand cache is enabled, the FLUSH transaction checks the

operand cache and if the hit line is dirty, then the data is written back to the external memory.

If the transaction is not hit to the cache or the hit entry is not dirty, it is no-operation.

This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a

cache miss. If it is known that a cache miss will result from a read or write operation, it is possible

to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss

due to the read or write operation, and so improve software performance. If a prefetch instruction

is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or

a protection violation, the result is no operation, and an exception is not generated. Details of the

prefetch instruction are given in the Programming Manual.

• Prefetch instruction (OC)

• Prefetch instruction (IC)

Prefetch Operation

Rev. 1.00 Oct. 01, 2007 Page 205 of 1956

Section 7 Caches

REJ09B0256-0100