r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1632

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 36 USB Function Controller (USBF)
36.4.3
EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads
without being aware of this dual-FIFO configuration.
When one FIFO is full after reception is completed, the IFR0/EP1 FULL bit is set. After the first
receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and
so the next packet can be received immediately. When both FIFOs are full, NACK is returned to
the host automatically. When reading of the receive data is completed following data reception, 1
is written to the TRG/EP1 RDFN bit. This operation empties the FIFO that has just been read, and
makes it ready to receive the next packet.
Rev. 1.00 Oct. 01, 2007 Page 1566 of 1956
REJ09B0256-0100
EP1 Bulk-Out Transfer (Dual FIFOs)
Clear EP1 FIFO full status
Data reception from host
Set EP1 FIFO full status
(IFR0/EP1 FULL = 1)
(IFR0/EP1 FULL = 0)
OUT token reception
EP1 FIFOs empty?
USB function
in EP1 FIFO?
Figure 36.10 EP1 Bulk-Out Transfer Operation
Space
Both
Yes
Yes
ACK
NAK
No
No
Interrupt request
Interrupt request
Read EP1 receive data
data register (EPDR1)
(TRG/EP1 RDFN = 1)
size register (EPSZ1)
Read data from EP1
Write 1 to EP1 read
Application
complete bit