r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 253

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte
operand cache (OC) for data.
7.1
The features of the cache are given in table 7.1.
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory. The features of the store queues are given in table 7.2.
Table 7.1
Table 7.2
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Item
Capacity
Addresses
Write
Write-back
Access right
Features
Cache Features
Store Queue Features
Instruction Cache
32-Kbyte cache
4-way set-associative, virtual
address index/physical address tag
32 bytes
256 entries/way

LRU (least-recently-used) algorithm LRU (least-recently-used) algorithm
Store Queues
32 bytes × 2
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
When MMU is disabled: Determined by SQMD bit in MMUCR
When MMU is enabled: Determined by PR for each page
Section 7 Caches
Rev. 1.00 Oct. 01, 2007 Page 187 of 1956
Operand Cache
32-Kbyte cache
4-way set-associative, virtual
address index/physical address tag
32 bytes
256 entries/way
Copy-back/write-through selectable
Section 7 Caches
REJ09B0256-0100