r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1577

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

IFR3 is an interrupt flag register for EP4 TS, EP4 TF, EP5 TS, and EP5 TR. When each flag is set

to 1 and an interrupt is enabled in the corresponding bit of IER3, an interrupt request (USBFI0 or

USBFI1) specified by the corresponding bit in ISR3 is issued to INTC.

Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear

bits, access the register so that 0 should be written only to the bits for the interrupt sources to be

cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C

language to clear bits.

Initial value:

Interrupt Flag Register 3 (IFR3)

Initial Value

R/W Description

R/W Set Interface Command Detection

R/W Description

[Setting condition]

When the valid Set Interface command is detected.

[Clearing conditions]

These bits are always read as undefined value. Write

value should always be 0.

These bits are always read as 0. The write value

should always be 0.

When 0 is written to by CPU

Section 36 USB Function Controller (USBF)

Rev. 1.00 Oct. 01, 2007 Page 1511 of 1956

REJ09B0256-0100