r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1120

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 26 I

In order to set up the master interface to transmit a data packet on the I

1. SCL clock generation divider (SCGD) = H'03

2. Clock division ratio (CDF) = H'3

1. Master address register = address of slave being accessed and STM1 bit (write mode: 0)

2. Transmit data register = first data byte to be transmitted

3. Master control register = H'89

1. Wait for master event (an interrupt of the MAT and MDE bits in the master status register).

2. Set the master control register to H'88 (To suspend the data transmission, the master device

3. Reset the MAT bit.

1. Wait for master event, MDE in the master status register.

2. Transmit data register = subsequent data.

Rev. 1.00 Oct. 01, 2007 Page 1054 of 1956

REJ09B0256-0100

(SCL frequency of 400 kHz)

(The peripheral clock is 66.7 MHz and the IIC's internal clock IICck is 16.7 MHz.)

(MDBS = 1, MIE = 1, ESG = 1)

will hold the SCL low until the MDE bit is cleared.)

If only one byte of data is transmitted, set the master control register to H'8A, meaning that the

stop generation is enabled. This generates a stop on the bus as soon as one byte has been

transmitted.

Load Clock Control Register

Load Master Control Register (First Data Byte and Address)

Wait for Outputting Address

Monitor Transmission of Data

Programming Examples

Master Transmitter

C Bus Interface (IIC)

C bus, follow the following