r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1283
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
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29.4
29.4.1
(1)
The following modes are available as the SIOF clock mode.
• Slave mode: SIOF_SCK, SIOF_SYNC input
• Master mode: SIOF_SCK, SIOF_SYNC output
(2)
In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock. The
division ratio is from 1/1 to 1/1024.
Note that, when using master clock directly as the serial clock without division by BRG (division
ratio: 1/1), the MSIMM bit in SISCR should be set to 1.
Figure 29.2 shows connections for supply of the serial clock.
Table 29.5 shows an example of serial clock frequency.
Master/Slave Modes
Baud Rate Generator
Operation
Serial Clocks
SIOF_MCLK
SIOF_SCK
Pck
Master clock
Figure 29.2 Serial Clock Supply
Baud rate generator
Pre-
scalar
Divider
1/1 to 1/1024
Master clock
Rev. 1.00 Oct. 01, 2007 Page 1217 of 1956
Section 29 Serial I/O with FIFO (SIOF)
Timing
control
SCKE
Master
REJ09B0256-0100
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