r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 202

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 5 Exception Handling
2. The user break is not accepted by the instruction in the delay slot of the RTE instruction.
(5)
1. When the MD or BL bit in the SR register is changed by the LDC instruction, the acceptance
Note: * When the LDC instruction for SR is executed, following instructions are fetched again
Rev. 1.00 Oct. 01, 2007 Page 136 of 1956
REJ09B0256-0100
bit. The completion type exception is accepted before branching to the destination of RTE
instruction. However, if the re-execution type exception is occurred, the operation cannot be
guaranteed.
of the exception is determined by the changed SR value, starting from the next instruction.* In
the completion type exception, an exception is accepted after the next instruction has been
executed. However, an interrupt of completion type exception is accepted before the next
instruction is executed.
Changing the SR register value and accepting exception
and the instruction fetch exception is evaluated again by the changed SR.

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