r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 787

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

20.3.3
The TIOR registers are 16-bit registers that control the TPU_TO pin. The TPU has four TIOR
registers, one for each channel. The TIOR registers are initialized to H'0000 by a reset, but not
initialized in standby mode, sleep mode, or module standby.
Care is required since TIOR is affected by the TMDR setting.
If the counting operation is halted, the initial value set by this register is output from the TPU_TO
pin.
Bit
15 to 3 
2 to 0
TIOR register settings should be made only when TCNT operation is halted.
Initial value:
R/W:
Bit:
Bit Name
IOA[2:0]
Timer I/O Control Registers (TIOR)
15

R
0
14

R
0
Initial
Value
All 0
000
13

R
0
12

R
0
R/W
R
R/W
11

R
0
Description
Reserved
These bits are always read as 0 and cannot be modified.
I/O Control
Bits IOA3 to IOA0 specify the functions of TGRA and the
TPU_TO pin. For details, see table 20.7.
10

R
0

R
9
0

R
8
0

R
7
0
Rev. 1.00 Oct. 01, 2007 Page 721 of 1956
Section 20 16-Bit Timer Pulse Unit (TPU)

R
6
0

R
5
0

R
4
0

R
3
0
REJ09B0256-0100
R/W
2
0
IOA[2:0]
R/W
1
0
R/W
0
0