r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 261

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

7.2.4
RAMCR controls the number of ways in the IC and OC.
RAMCR modifications must only be made by a program in the non-cacheable P2 area. After
RAMCR has been updated, execute one of the following three methods before an access
(including an instruction fetch) to the cacheable area or the L memory area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the R2 bit in IRMCR is 0 (initial value) before updating RAMCR, the specific instruction
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
Initial value:
Initial value:
Bit
31 to 10
9
non-cacheable area or the L memory area.
does not need to be executed. However, note that the CPU processing performance will be
lowered because the instruction fetch is performed again for the next instruction after RAMCR
has been updated.
R/W:
R/W:
Bit:
Bit:
On-Chip Memory Control Register (RAMCR)
Bit Name

RMD
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
26
10
R
R
0
0
RMD
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
On-Chip Memory Access Mode Bit
For details, see section 8.4, L Memory Protective
Functions.
R/W
25
R
0
9
0
R/W
RP
24
R
0
8
0
IC2W OC2W
R/W
23
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 195 of 1956
R/W
22
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
Section 7 Caches
REJ09B0256-0100
18
R
R
2
0
0
17
R
R
0
1
0
16
R
R
0
0
0