r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1375

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

DTBUSY_TU Undefined

Command Register Write Enable

Indicates whether the CMDR command is being

transmitted or has been transmitted.

0: The CMDR command has been transmitted, or the

1: The CMDR command is waiting to be transmitted or

Indicates command execution status. Indicates that the

card is in the busy state after the command sequence

of a command without data transfer which includes the

busy state in the response has ended or a command

with write data has ended.

0: Idle state waiting for a command, or command

1: Card is in the data busy state after command

Data Busy Pin Status

Monitors the levels of the DAT pin in MMC mode. By

reading this bit, whether the card is in the busy state

can be monitored after the card in the busy state has

been deselected and then selected again afterwards.

0: Card indicates data busy.

1: Card indicates not data busy.

This bit is always read as 0. The write value should

always be 0.

Interrupt Request

Indicates whether an interrupt is requested. An interrupt

request is the logical OR of the INTSTR0, INTSTR1,

and INTSTR2 flags. Settings of the INTSTR0,

INTSTR1, and INTSTR2 flags are controlled by the

enable bits in INTCR0, INTSTR1, and INTCR2.

0: No interrupt requested.

1: Interrupt requested.

START bit in CMDSTRT has not been set yet, so the

new command can be written.

is being transmitted. If a new command is written, a

malfunction will result.

sequence execution in progress

sequence termination.

Section 31 Multimedia Card Interface (MMCIF)

Rev. 1.00 Oct. 01, 2007 Page 1309 of 1956

REJ09B0256-0100