r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 785

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

20.3.2
The TMDR registers are 16-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has four TMDR registers, one for each channel. The TMDR registers
are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module
standby.
TMDR register settings should be made only when TCNT operation is stopped.
Bit
15 to 7 
6
5
4
Initial value:
R/W:
Bit:
Bit Name
BFWT
BFB
BFA
Timer Mode Registers (TMDR)
15

R
0
14

R
0
Initial
Value
All 0
0
0
0
13

R
0
12

R
0
R/W
R
R/W
R/W
R/W
11

R
0
Description
Reserved
These bits are always read as 0 and cannot be modified.
Buffer Write Timing
Specifies TGRA and TGRB update timing when TGRC and
TGRD are used as a compare match buffer. When TGRC
and TGRD are not used as a compare match buffer register,
this bit does not function.
0: TGRA and TGRB are rewritten at compare match of each
1: TGRA and TGRB are rewritten in counter clearing.
Buffer Operation B
Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer
operation.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation*
Buffer Operation A
Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer
operation.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
10

R
0
register.

R
9
0

R
8
0

R
7
0
BFWT BFB
Rev. 1.00 Oct. 01, 2007 Page 719 of 1956
R/W
Section 20 16-Bit Timer Pulse Unit (TPU)
6
0
R/W
5
0
R/W
BFA
4
0

R
3
0
REJ09B0256-0100
R/W
2
0
MD[2:0]
R/W
1
0
R/W
0
0