r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1280

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 29 Serial I/O with FIFO (SIOF)
29.3.12 Receive Data Assign Register (SIRDAR)
SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a
frame.
Rev. 1.00 Oct. 01, 2007 Page 1214 of 1956
REJ09B0256-0100
Initial value:
Bit
5, 4
3 to 0
Bit
15
14 to 12 —
11 to 8
R/W:
BIt:
Bit Name
—
TDRA[3:0]
Bit Name
RDLE
RDLA[3:0]
RDLE
R/W
15
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
0000
Initial
Value
0
All 0
0000
12
—
R
0
R/W
R/W
R/W
R
R/W
R/W
R
R/W
11
0
R/W
RDLA[3:0]
10
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a transmit
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Description
Receive Left-Channel Data Enable
0: Disables left-channel data reception
1: Enables left-channel data reception
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
R/W
0
9
Transmit data for the right channel is specified in
the SITDR bit in SITDR.
Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
R/W
8
0
RDRE
R/W
7
0
—
R
6
0
—
R
5
0
—
R
4
0
R/W
3
0
RDRA[3:0]
R/W
2
0
R/W
1
0
R/W
0
0