r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 329
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
- Current page: 329 of 2026
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9.3.11
NMIFCR is a 32-bit readable and partially writable with conditions register that has an NMI flag
(NMIFL bit) that can be read or cleared by software. The NMIFL bit is automatically set to 1 by
hardware when an NMI interrupt is detected by the INTC. To clear the NMIFL bit, write 0 to the
bit by software.
The NMIFL bit value does not affect NMI acceptance by the CPU. Although the NMI request
detected by the INTC is cleared by CPU acceptance, the NMIFL bit is not cleared automatically.
Even if 0 is written to the NMIFL bit before the NMI request is accepted by the CPU, the NMI
request is not canceled.
Initial value:
Initial value:
Bit
31
30 to 17 —
R/W:
R/W:
Bit:
Bit:
NMI Flag Control Register (NMIFCR)
Bit Name
NMIL
NMIL
31
15
−
R
R
0
30
−
14
−
R
R
0
0
Initial
Value
Undefined R
All 0
29
13
−
R
−
R
0
0
28
12
−
−
R
R
0
0
27
11
−
R/W
R
R
−
R
0
0
26
10
−
−
R
R
0
0
Description
NMI Input Level
Indicates the level of the signal input at the NMI pin.
This bit can be read to determine the NMI pin level.
This bit cannot be modified.
0: Low level is input to the NMI pin
1: High level is input to the NMI pin
Reserved
These bits are always read as 0. The write value should
always be 0.
25
−
−
R
R
0
9
0
24
−
R
−
R
0
8
0
23
−
R
−
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 263 of 1956
22
−
−
R
R
0
6
0
Section 9 Interrupt Controller (INTC)
21
−
−
R
R
0
5
0
20
−
−
R
R
0
4
0
19
−
−
R
R
0
3
0
REJ09B0256-0100
18
−
−
R
R
0
2
0
17
−
−
R
R
0
1
0
NMIFL
R/W
16
−
R
0
0
0
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