r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1303
r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
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(2)
Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data,
and frame length = 16 bits
(3)
Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data,
and frame length = 64 bits
SIOF_SYNC
SIOF_RXD
SIOF_SCK
SIOF_TXD
8-bit Monaural Data (Case 2)
16-bit Monaural Data
SIOF_RXD
SIOF_SCK
SIOF_SYNC
SIOF_TXD
Figure 29.14 Transmit and Receive Timing (8-Bit Monaural Data (2))
Figure 29.15 Transmit and Receive Timing (16-Bit Monaural Data)
Specifications:
Specifications:
L-channel data
1-bit delay
Slot No.0
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 0,
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 0,
1-bit delay
L-channel data
Slot No.0
Slot No.1
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
1 frame
1 frame
Slot No.2
Slot No.1
Rev. 1.00 Oct. 01, 2007 Page 1237 of 1956
FL[3:0] = 0100 (frame length: 16 bits)
TDRE = 0,
RDRE = 0,
CD1E = 0,
FL[3:0] = 1101 (frame length: 64 bits)
TDRE = 0,
RDRE = 0,
CD1E = 0,
Section 29 Serial I/O with FIFO (SIOF)
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000
Slot No.3
REJ09B0256-0100
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