r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1868

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 42 User Debugging Interface (H-UDI)

The H-UDI has the following registers.

Table 42.3 Register Configuration (1)

Notes: 1. The area P4 address is an address when accessing through area P4 in a virtual

Table 42.4 Register Configuration (2)

Table 42.5 Register Status in Each Processing State

Rev. 1.00 Oct. 01, 2007 Page 1802 of 1956

REJ09B0256-0100

Instruction register

Interrupt source register

Boundary scan register

Bypass register

Instruction register

Interrupt source register

Boundary scan register

Bypass register

Instruction register

Interrupt source register SDINT

2. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller

1. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller

2. When reading via the H-UDI, the value is always H'FFFF FFFD.

3. Only 1 can be written to the LSB by the H-UDI interrupt command.

address space. The area 7 address is an address when accessing through area 7 in a

physical space using the TLB.

initializes to these values.

Power-On Reset

Manual Reset Sleep

Area 7 Address*

Initial Value*

H'FFFF FFFD (fixed value*