r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 927

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.3.42 Relay Status Register (TSU_FWSR)
TSU_FWSR is a 32-bit readable/writable register that indicates the status during relay operations.
By setting the relay status interrupt mask register (TSU_FWINMK), this status can be notified to
the CPU as an interrupt source. The status bit set to 1 will be cleared to 0 by writing 1 to the
corresponding bit. (The status bit retains the value until it is cleared to 0.)
Interrupts generated due to this status register are identified as EINT2. For details on the priority
order of interrupts, see section 9.4.6, Interrupt Exception Handling and Priority in section 9,
Interrupt Controller (INTC).
If an error other than RBSY1 or RBSY0 occurs during relay operations, the corresponding relay
frame is discarded.
Bit
31 to 24
23
22
21
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

OVF0
RBSY0
RINT60
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
0
0
28
12


R
R
0
0
27
11


R
R
0
0
R/W
R
R/W
R/W
R/W
26
10


R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Port 0-to-1 Relay FIFO Overflow Detect
Set to 1 when the port 0-to-1 relay FIFO overflows.
E-MAC-0 Overflow Alert Signal Output
Set to 1 when the threshold of TSU_BSYSL0 is valid
and exceeded.
E-MAC-0 Carrier Extension Loss Error Detect
Set to 1 when a frame with the carrier extension lost is
received in the E-MAC-0.
25

R

R
0
9
0
24

R

R
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
OVF0
OVF1
R/W
R/W
23
0
7
0
RBSY
RBSY
R/W
R/W
Rev. 1.00 Oct. 01, 2007 Page 861 of 1956
22
0
6
0
0
1
RINT
R/W
R/W
RINT
21
60
61
0
5
0
RINT
R/W
R/W
RINT
20
50
51
0
4
0
RINT
R/W
R/W
RINT
19
40
41
0
3
0
REJ09B0256-0100
RINT
R/W
RINT
R/W
18
30
31
0
2
0
RINT
R/W
RINT
17
20
21
0
1
0
R/W
RINT
RINT
R/W
16
10
11
0
0
0