r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1240

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)

SCIF Interrupt Sources and the DMAC

The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receive-

error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt

(BRI) request.

Table 28.9 shows the interrupt sources and their order of priority. The interrupt sources are

enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt

request is sent to the interrupt controller for each of these interrupt sources.

If the TDFE flag in SCFSR is set to 1 when a TXI interrupt is enabled by the TIE bit, a TXI

interrupt request and a transmit-FIFO-data-empty request for DMA transfer are generated. If the

TDFE flag is set to 1 when a TXI interrupt is disabled by the TIE bit, only a transmit-FIFO-data-

empty request for DMA transfer is generated. A transmit-FIFO-data-empty request can activate

the DMAC to perform data transfer.

If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit, an

RXI interrupt request and a receive-FIFO-data-full request for DMA transfer are generated. If the

RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit, only a receive-FIFO-

data-full request for DMA transfer is generated. A receive-FIFO-data-full request can activate the

DMAC to perform data transfer. Note that generation of an RXI interrupt request or a receive-

FIFO-data-full request by setting the DR flag to 1 occurs only in asynchronous mode.

When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is

generated. If transmission/reception is carried out using the DMAC, set and enable the DMAC

before making the SCIF settings. Also make settings to inhibit output of RXI and TXI interrupt

requests to the interrupt controller. If output of interrupt requests is enabled, these interrupt

requests to the interrupt controller can be cleared by the DMAC regardless of the interrupt

By setting the REIE bit to 1 while the RIE bit is cleared to 0 in SCSCR, it is possible to output

ERI interrupt requests, but not RXI interrupt requests.

Rev. 1.00 Oct. 01, 2007 Page 1174 of 1956

REJ09B0256-0100