r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 475

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

The memory controller is a module that arbitrates accesses from the CPU and modules and outputs
control signals for the DDR-SDRAM. This module allows direct connection with the DDR-
SDRAM. This module is provided with two interface modules (SHIF: SuperHyway bus interface
and LCDIF: LCD interface) and one DDR-SDRAM controller (DDRC), and an arbiter (ARBT)
that arbitrates accesses from interface modules to the DDRC.
12.1
• The data bus width of the DDRIF is 32 bits
• Supports DDR-SDRAM self-refreshing
• Supports the DDR266 (133MHz); DDR200 (100MHz)
• Efficient data transfer is possible using the SuperHyway bus (Internal bus)
• Supports a 4-bank DDR-SDRAM
• Supports a burst length of 2
• Connectable memory size: 256 Mbits, 512 Mbits, 1 Gbit, and 2 Gbits
• Big or little endian for external memory access can be switched at a power-on reset
Address × bit width (bit) for supported memory is as follows.
DDR-SDRAM data bus width is 32 bits:
 Parallel connection of two 128-Mbit DDRs (× 16) (Total size 256-Mbits)
 Parallel connection of two 256-Mbit DDRs (× 16) (Total size 512-Mbits)
 Parallel connection of two 512-Mbit DDRs (× 16) (Total size 1-Gbit)
 Parallel connection of two 1-Gbit DDRs (× 16) (Total size 2-Gbits)
Features
Section 12 DDR-SDRAM Interface (DDRIF)
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 1.00 Oct. 01, 2007 Page 409 of 1956
REJ09B0256-0100