r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 631

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

This LSI includes the direct memory access controller (DMAC).

The DMAC can be used in place of the CPU to perform high-speed transfers between external

devices that have DACK (transfer request acknowledge signal), external memory, on-chip

memory, memory-mapped external devices, and on-chip peripheral modules.

• Six channels (four channels can receive an external request: channel 0 to 3)

• 4-Gbyte physical address space

• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), 16 bytes, and 32

• Maximum transfer count: 16,777,216 transfers

• Address mode: Dual address mode

• Transfer requests:

• Selectable bus modes:

• Selectable channel priority levels:

• Interrupt request: An interrupt request can be generated to the CPU after half of the transfers

• External request detection: There are following four types of DREQn input detection.

External request (channel 0 to 3), on-chip peripheral module request (channel 0 to 5), or auto

request can be selected.

The following modules can issue an on-chip peripheral module request.

 CMT, SCIF0, SCIF1, SCIF2, HAC, USBF, SSI0 to SSI3, MMCIF, SIM, SIOF0 to SIOF2,

Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.

The channel priority levels are selectable between fixed mode and round-robin mode.

ended, all transfers ended, or an address error occurred.

(n = 0 to 3)

 Low level detection (Initial value)

 High level detection

 Rising edge detection

 Falling edge detection

Section 14 Direct Memory Access Controller (DMAC)

STIF0 and STIF1

Section 14 Direct Memory Access Controller (DMAC)

Rev. 1.00 Oct. 01, 2007 Page 565 of 1956

REJ09B0256-0100