R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1022

MCU FLASH 384K ROM 144-LQFP

R5F61663RN50FPV

Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheets

Specifications of R5F61663RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 USB Function Module (USB)
Rev. 2.00 Sep. 24, 2008 Page 988 of 1468
REJ09B0412-0200
Bit
0
Bit Name
EP1DMAE
Initial
Value
0
R/W
R/W
Endpoint 1 DMA Transfer Enable
Description
When this bit is set, a DMAC start interrupt signal
(USBINTN0) is asserted and DMA transfer is enabled
from the endpoint 1 receive FIFO buffer to memory. If
there is at least one byte of receive data in the FIFO
buffer, the DMAC start interrupt signal (USBINTN0) is
asserted. In DMA transfer, when all the received data
is read, EP1 is automatically read and the completion
trigger operates.
EP1-related interrupt requests to the CPU are not
automatically masked.
1. Write of 1 to the EP1 DMAE bit in DMA
2. Set the DMAC to activate through USBINTN0
3. Transfer count setting in the DMAC
4. DMAC activation
5. DMA transfer
6. DMA transfer end interrupt generated
See section 20.8.2, DMA Transfer for Endpoint 1.
Operating procedure:

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