R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 167
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.3.2
CPUPCR sets whether or not the CPU has priority over the DTC, DMAC and EXDMAC. The
interrupt exception handling by the CPU can be given priority over that of the DTC, DMAC and
EXDMAC transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR.
The priority level of the DMAC and EXDMAC is set by the DMAC and EXDMAC control
register for each channel.
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
Bit Name
CPUPCE
DTCP2
DTCP1
DTCP0
CPU Priority Control Register (CPUPCR)
CPUPCE
R/W
7
0
Initial
Value
0
0
0
0
DTCP2
R/W
6
0
R/W
R/W
R/W
R/W
R/W
DTCP1
R/W
5
0
CPU Priority Control Enable
Description
Controls the CPU priority control function. Setting this bit
to 1 enables the CPU priority control over the DTC,
DMAC and EXDMAC.
0: CPU always has the lowest priority
1: CPU priority control enabled
DTC Priority Level 2 to 0
These bits set the DTC priority level.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
DTCP0
R/W
4
0
IPSETE
R/W
3
0
Rev. 2.00 Sep. 24, 2008 Page 133 of 1468
CPUP2
R/(W)*
2
0
Section 7 Interrupt Controller
CPUP1
R/(W)*
1
0
REJ09B0412-0200
CPUP0
R/(W)*
0
0
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