R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 14

• Manufacturer Part Number: R5F61663RN50FPV
• Description: MCU FLASH 384K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61663RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7
6.8
6.9
Section 7 Interrupt Controller............................................................................ 129
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Rev. 2.00 Sep. 24, 2008 Page xii of xxxii
Instruction Exception Handling ........................................................................................ 124
6.7.1
6.7.2
6.7.3
Stack Status after Exception Handling ............................................................................. 127
Usage Note ....................................................................................................................... 128
Features............................................................................................................................. 129
Input/Output Pins.............................................................................................................. 131
Register Descriptions........................................................................................................ 131
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Interrupt Sources............................................................................................................... 147
7.4.1
7.4.2
Interrupt Exception Handling Vector Table...................................................................... 149
Interrupt Control Modes and Interrupt Operation............................................................. 156
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
CPU Priority Control Function Over DTC, DMAC and EXDMAC ................................ 165
Usage Notes ...................................................................................................................... 168
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
Trap Instruction ................................................................................................ 124
Sleep Instruction Exception Handling .............................................................. 125
Exception Handling by Illegal Instruction ........................................................ 126
Interrupt Control Register (INTCR) ................................................................. 132
CPU Priority Control Register (CPUPCR) ....................................................... 133
Interrupt Priority Registers A to O, Q, and R (IPRA to IPRO, IPRQ, and
IPRR) ................................................................................................................ 135
IRQ Enable Register (IER) ............................................................................... 137
IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 138
IRQ Status Register (ISR)................................................................................. 144
Software Standby Release IRQ Enable Register (SSIER) ................................ 145
External Interrupts ............................................................................................ 147
Internal Interrupts ............................................................................................. 148
Interrupt Control Mode 0.................................................................................. 156
Interrupt Control Mode 2.................................................................................. 158
Interrupt Exception Handling Sequence ........................................................... 160
Interrupt Response Times ................................................................................. 161
DTC and DMAC Activation by Interrupt ......................................................... 162
Conflict between Interrupt Generation and Disabling ...................................... 168
Instructions that Disable Interrupts................................................................... 169
Times when Interrupts are Disabled ................................................................. 169
Interrupts during Execution of EEPMOV Instruction ...................................... 169
Interrupts during Execution of MOVMD and MOVSD Instructions................ 169
Interrupts of Peripheral Modules ...................................................................... 170