R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 313

MCU FLASH 384K ROM 144-LQFP

R5F61663RN50FPV

Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheets

Specifications of R5F61663RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.9.10
For DMAC or EXDMAC single address transfers, the DACK and EDACK signal assert timing
can be modified by using bits DKC and EDKC in BCR1.
Figure 9.37 shows the DACK and EDACK signal output timing. Setting the DKC bit or the
EDKC bit to 1 asserts the DACK or EDACK signal a half cycle earlier.
DACK and EDACK Signal Output Timing
RDNn = 0
RDNn = 1
DACK or
EDACK
Figure 9.37 DACK and EDACK Signal Output Timing
Address bus
CSn
AH
RD
D15 to D0
RD
D15 to D0
BS
RD/WR
DKC, EDKC = 0
DKC, EDKC = 1
Note: n = 3 to 7
T
ma1
Address cycle
Address
Address
T
ma2
Rev. 2.00 Sep. 24, 2008 Page 279 of 1468
Data cycle
T
1
Section 9 Bus Controller (BSC)
Read
data
Read data
T
2
REJ09B0412-0200

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