R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 198
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Interrupt Controller
to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or
DMAC may not be activated, and the data transfer may not be performed.
(2)
The DTC activation source is selected according to the default priority, and the selection is not
affected by its mask level or priority level. For respective priority levels, see table 12.1, Interrupt
Sources, DTC Vector Addresses, and Corresponding DTCEs.
(3)
If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the
CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is
selected as the DTC, DMAC or EXDMAC activation source or CPU interrupt source, respective
operations are performed independently.
Table 7.6 lists the selection of interrupt sources and interrupt source clear control by setting the
DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the
DISEL bit in MRB of the DTC.
Table 7.6
[Legend]
√: The corresponding interrupt is used. The interrupt source is cleared.
O: The corresponding interrupt is used. The interrupt source is not cleared.
X: The corresponding interrupt is not available.
*: Don't care.
(4)
The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in
table 7.6, when the DTC or DMAC reads/writes the prescribed register.
Rev. 2.00 Sep. 24, 2008 Page 164 of 1468
REJ09B0412-0200
DMAC
DTA
0
1
(The interrupt source flag must be cleared in the CPU interrupt handling routine.)
Priority Determination
Operation Order
Usage Note
Interrupt Source Selection and Clear Control
DTCE
0
1
*
Setting
DTC
DISEL
*
0
1
*
DMAC
O
O
O
√
Interrupt Source Selection/Clear Control
DTC
X
√
O
X
CPU
√
X
√
X
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