R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 627
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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12.9.5
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. At this time, SCI and A/D converter
interrupt/activation sources, are cleared when the DTC reads or writes to the relevant register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation source
will be retained.
12.9.6
The transfer information start address to be specified in the vector table should be address 4n. If an
address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s.
The source and destination addresses specified in SAR and DAR, respectively, will be transferred
in the divided bus cycles depending on the address and data size.
12.9.7
When IBCCS = 1 and the DMAC is used, clear the IBCCS bit to 0 and then set to 1 again before
modifying the DTC transfer information in the CPU exception handling routine initiated by a DTC
transfer end interrupt.
12.9.8
The DTC supports big and little endian formats. The endian formats used when transfer
information is written to and when transfer information is read from by the DTC must be the
same.
Chain Transfer
Transfer Information Start Address, Source Address, and Destination Address
Transfer Information Modification
Endian Format
Rev. 2.00 Sep. 24, 2008 Page 593 of 1468
Section 12 Data Transfer Controller (DTC)
REJ09B0412-0200
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