R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 911
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit
7
6
5
4
3
2
Bit Name
C/A
CHR
PE
O/E
STOP
MP
0
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode*
Character Length (valid only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed and
In clocked synchronous mode, a fixed data length of 8
bits is used.
Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. For a multiprocessor format, parity bit addition
and checking are not performed regardless of the PE bit
setting.
Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
Stop Bit Length (valid only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the next
transmit frame.
Multiprocessor Mode (valid only in asynchronous mode)
When this bit is set to 1, the multiprocessor function is
enabled. The PE bit and O/E bit settings are invalid in
multiprocessor mode.
the MSB (bit 7) in TDR is not transmitted in
transmission.
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Sep. 24, 2008 Page 877 of 1468
REJ09B0412-0200
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