R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 535
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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When EDDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. Do not write to
EDDAR for a channel on which a transfer operation is in progress.
(3)
When an EXDMA transfer is performed, the value in EDTCR is decremented by the number of
bytes transferred. When a byte is transferred, the value is decremented by 1; when a word is
transferred, the value is decremented by 2; when a longword is transferred, the value is
decremented by 4. However, when the EDTCR value is 0, transfers are not counted and the
EDTCR value does not change.
All of the bits of EDTCR may change, so when EDTCR is read by the CPU during EXDMA
transfer, a longword access must be used. During a transfer operation, EDTCR may be updated
without regard to accesses from the CPU, and the correct values may not be read if the upper and
lower words are read separately. Do not write to EDTCR for a channel on which a transfer
operation is in progress.
If there is conflict between an address update associated with EXDMA transfer and a write by the
CPU, the CPU write has priority.
In the event of conflict between an EDTCR update from 1, 2, or 4 to 0 and a write (of a nonzero
value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is
terminated.
(4)
EDBSR is valid in block transfer or repeat transfer mode. EDBSR31 and EDBSR16 are used as
BKSZH and EDBSR15 and EDBSR0 for BKSZ. The 16 bits of BKSZH holds a block size and
repeat size and their values do not change. The 16 bits of BKSZ functions as a block size or repeat
size counter, the value of which is decremented by 1 when one data transfer is performed. When
the BKSZ value is determined as 0 during EXDMA transfer, the EXDMAC does not store 0 in
BKSZ and stores the BKSZH value.
The upper 16 bits of EDBSR is never updated, allowing a word-size access.
Do not write to EDBSR for a channel on which a transfer operation is in progress.
EXDMA Transfer Count Register (EDTCR)
EXDMA Block Size Register (EDBSR)
Rev. 2.00 Sep. 24, 2008 Page 501 of 1468
Section 11 EXDMA Controller (EXDMAC)
REJ09B0412-0200
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