R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 352
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Bus Controller (BSC)
9.11.10 Controlling Write-Precharge Delay
In an SDRAM write cycle, a certain time is required until the write operation is completed inside
of the SDRAM. When the time between the WRIT command and the subsequent PALL command
does not meet a given specification, the Trwl cycle can be inserted for one cycle by the TRWL bit
in SDCR. Whether or not to insert the Trwl cycle depends on the SDRAM to be used and the
frequency of this LSI.
Figure 9.68 shows a timing example when one Trwl cycle is inserted.
Rev. 2.00 Sep. 24, 2008 Page 318 of 1468
REJ09B0412-0200
Figure 9.68 Write Timing Example when Write-Precharge Delay Cycle Insertion
Precharge-sel
Address bus
D15 to D8
SDRAMφ
D7 to D0
DQMLU
DQMLL
RD/WR
RAS
CAS
CKE
WE
CS
BS
PALL
T
Row address
p
(TRWL = 1)
High
address
ACTV
Row
T
r
NOP
T
c1
Column address
WRIT
T
c2
NOP
T
rwl
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