R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 401
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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9.16
This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI
incorporates internal access and external access bus arbiters that can be used and controlled
independently. The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The external
bus arbiter handles the external access by the CPU, DTC, DMAC, and EXDMAC, refresh, and
external bus release request (external bus master).
The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means
of the bus request acknowledge signal.
9.16.1
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The priority of the internal bus arbitration:
The priority of the external bus arbitration:
If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC or DTC
to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this
case, the priority between the DMAC and DTC does not change. If an external bus release request,
an EXDMAC access, and a refresh cycle request continue, an external bus access by the CPU,
DTC, and DMAC can be given priority to execute the bus cycles alternatively between them by
setting the EBCCS bit in BCR2. In this case, the priorities among the refresh, EXDMAC, and
external bus release request do not change.
An internal bus access by internal bus masters and an external bus access by an external bus
release request, a refresh cycle, or an EXDMAC access can be executed in parallel.
DMAC > DTC > CPU
Refresh > EXDMAC > External bus release request > External access by the CPU, DTC, or
DMAC
Bus Arbitration
Operation
Rev. 2.00 Sep. 24, 2008 Page 367 of 1468
Section 9 Bus Controller (BSC)
REJ09B0412-0200
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