R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 760
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 16-Bit Timer Pulse Unit (TPU)
Note:
Rev. 2.00 Sep. 24, 2008 Page 726 of 1468
REJ09B0412-0200
Bit
1
0
*
Bit Name
TGFB
TGFA
Only 0 can be written to clear the flag.
Initial
value
0
0
R/W
R/(W)* Input Capture/Output Compare Flag B
R/(W)* Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRB input
capture or compare match.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Status flag that indicates the occurrence of TGRA input
capture or compare match.
[Setting conditions]
•
•
[Clearing conditions]
•
•
•
Description
When TCNT = TGRB while TGRB is functioning as
output compare register
When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
When DTC is activated by a TGIB interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFB after reading TGFB = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When TCNT = TGRA while TGRA is functioning as
output compare register
When TCNT value is transferred to TGRA by input
capture signal while TGRA is functioning as input
capture register
When DTC is activated by a TGIA interrupt while the
DISEL bit in MRB of DTC is 0
When DMAC is activated by a TGIA interrupt while
the DTA bit in DMDR of DMAC is 1
When 0 is written to TGFA after reading TGFA = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
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