R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 553
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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When the NRD bit is set to 1 in EDMDR, the acceptance timing of the next transfer request can be
delayed one cycle later.
Figure 11.38 shows an example of single address mode transfer activated by the EDREQ pin low
level with NRD = 1 specified.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes
when one cycle of the request clearance period specified by NRD = 1 expires and EDREQ pin low
level sampling is performed again. This sequence of operations is repeated until the end of the
transfer.
Bφ
EDREQ
Address bus
Channel
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of write cycle plus one cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
EDREQ Pin Low Level Activation Timing with NRD = 1 Specified
Figure 11.38 Example of Single Address Mode Transfer Activated
[1]
Request
release
Minimum 3 cycles
Bus
by EDREQ Pin Low Level with NRD = 1 Specified
[2]
Request clearance period
[3]
EXDMA single
Transfer destination
Transfer source/
Extended request clearance
Acceptance resumed
period specified by NRD
[4]
Request
Minimum 3 cycles
release
[5]
Bus
Rev. 2.00 Sep. 24, 2008 Page 519 of 1468
Section 11 EXDMA Controller (EXDMAC)
Request clearance period
[6]
EXDMA single
Extended request clearance
Transfer destination
Transfer source/
period specified by NRD
Acceptance resumed
release
Bus
REJ09B0412-0200
[7]
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