R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 738
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.3
TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one
each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin
should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
• TIORL_0, TORL_3
Rev. 2.00 Sep. 24, 2008 Page 704 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Timer I/O Control Register (TIOR)
IOD3
IOB3
R/W
R/W
7
0
7
0
IOD2
IOB2
R/W
R/W
6
0
6
0
IOB1
IOD1
R/W
R/W
5
0
5
0
IOD0
IOB0
R/W
R/W
4
0
4
0
IOA3
IOC3
R/W
R/W
3
0
3
0
IOA2
IOC2
R/W
R/W
2
0
2
0
IOA1
IOC1
R/W
R/W
1
0
1
0
IOA0
IOC0
R/W
R/W
0
0
0
0
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