R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1114

MCU FLASH 384K ROM 144-LQFP

R5F61663RN50FPV

Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheets

Specifications of R5F61663RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 22 A/D Converter
[Legend]
x:
Notes: 1. To set A/D conversion to start by the ADTRG0 pin, the DDR bit and ICR bit for the
Rev. 2.00 Sep. 24, 2008 Page 1080 of 1468
REJ09B0412-0200
Bit
3
2
1
Don't care
2. Pφ criterion
Bit Name
CKS1
CKS0
ADSTCLR 0
corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O
Ports.
Initial
Value
0
0
R/W
R/W
R/W
R/W
Description
Clock Select 1 and 0
These bits set the A/D conversion time in combination
with the EXCKS bit. First select the A/D conversion time
by setting bits CKS1 and CKS0 while ADST = 0 and then
set the mode of A/D conversion.
EXCKS, CKS1, and CKS0
000: A/D conversion time = 528 states*
001: A/D conversion time = 268 states*
010: A/D conversion time = 138 states*
011: A/D conversion time = 73 states*
100: A/D conversion time = 336 states*
101: A/D conversion time = 172 states*
110: A/D conversion time = 90 states*
111: A/D conversion time = 49 states*
A/D Start Clear
This bit enables or disables automatic clearing of the
ADST bit in scan mode.
0: The ADST bit is not automatically cleared to 0 in scan
1: Clears the ADST bit to 0 upon completion of the A/D
mode.
conversion for all of the selected channels in scan
mode.
2
2
2
2
2
2
(max.)
2
2
(max.)
(max.)
(max.)
(max.)
(max.)
(max.)
(max.)

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