R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 17

• Manufacturer Part Number: R5F61663RN50FPV
• Description: MCU FLASH 384K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61663RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.10
9.11
9.12
9.13
9.14
DRAM Interface ............................................................................................................... 280
9.10.1
9.10.2
9.10.3
9.10.4
9.10.5
9.10.6
9.10.7
9.10.8
9.10.9
9.10.10 Controlling Byte and Word Accesses ............................................................... 290
9.10.11 Burst Access Operation..................................................................................... 292
9.10.12 Refresh Control................................................................................................. 298
9.10.13 DRAM Interface and Single Address Transfer by DMAC and EXDMAC ...... 303
Synchronous DRAM Interface ......................................................................................... 306
9.11.1
9.11.2
9.11.3
9.11.4
9.11.5
9.11.6
9.11.7
9.11.8
9.11.9
9.11.10 Controlling Write-Precharge Delay .................................................................. 318
9.11.11 Controlling Byte and Word Accesses ............................................................... 319
9.11.12 Fast-Page Access Operation ............................................................................. 321
9.11.13 Refresh Control................................................................................................. 327
9.11.14 Setting SDRAM Mode Register ....................................................................... 335
9.11.15 SDRAM Interface and Single Address Transfer by DMAC and EXDMAC .... 336
9.11.16 EXDMAC Cluster Transfer .............................................................................. 344
Idle Cycle.......................................................................................................................... 347
9.12.1
9.12.2
Bus Release....................................................................................................................... 360
9.13.1
9.13.2
9.13.3
Internal Bus....................................................................................................................... 364
9.14.1
Setting DRAM Space........................................................................................ 280
Address Multiplexing........................................................................................ 280
Data Bus............................................................................................................ 281
I/O Pins Used for DRAM Interface .................................................................. 281
Basic Timing..................................................................................................... 282
Controlling Column Address Output Cycle...................................................... 283
Controlling Row Address Output Cycle ........................................................... 284
Controlling Precharge Cycle............................................................................. 286
Wait Control ..................................................................................................... 287
Setting SDRAM space ...................................................................................... 306
Address Multiplexing........................................................................................ 307
Data Bus............................................................................................................ 307
I/O Pins Used for DRAM Interface .................................................................. 308
Basic Timing..................................................................................................... 309
CAS Latency Control........................................................................................ 311
Controlling Row Address Output Cycle ........................................................... 313
Controlling Precharge Cycle............................................................................. 315
Controlling Clock Suspend Insertion................................................................ 317
Operation .......................................................................................................... 347
Pin States in Idle Cycle ..................................................................................... 359
Operation .......................................................................................................... 360
Pin States in External Bus Released State......................................................... 361
Transition Timing ............................................................................................. 362
Access to Internal Address Space ..................................................................... 364
Rev. 2.00 Sep. 24, 2008 Page xv of xxxii