R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1260
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 27 Clock Pulse Generator
Rev. 2.00 Sep. 24, 2008 Page 1226 of 1468
REJ09B0412-0200
Bit
7
6
5
4
3
2
1
0
Bit Name
EXSTP
WAKE32K
CK32K
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Main Clock Oscillation Stop
0: The main clock oscillator and PLL remain active
1: The main clock oscillator and PLL are stopped during
Wakeup Clock Select
Selects the operating clock for use as the system clock
after the transition from the subclock operation in
software standby mode has been initiated by an
interrupt.
0: On leaving software standby mode, the main clock is
1: On leaving software standby mode, the subclock is
Subclock Select
0: The system clock (Iφ), peripheral module clock (Pφ),
1: The system clock (Iφ), peripheral module clock (Pφ),
When the OSC32STP bit in TCR32K is 1, 1 cannot be
written to this bit. This bit is cleared to 0 when clearing
software standby mode while the value of WAKE32K
is 0. Dummy read of this bit must be performed twice
immediately after this bit is written to.
during subclock operation, but are stopped in
standby mode.
subclock operation.
the operating clock.
the operating clock. This setting is valid when bit 0
(CK32K) is set to 1.
and external bus clock (Bφ) operate on the main
clock.
and external bus clock (Bφ) operate on the subclock.
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