R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1093
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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21.4.6
The logic levels at the SCL and SDA pins are routed through the noise cancelers before being
latched internally. Figure 21.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The signal input to SCL
(or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
ICDRS
ICDRR
RDRF
SDA
SDA
SCL
SCL
User
Sampling clock
Noise Canceler
SDA input
SCL input
or
Figure 21.12 Slave Receive Mode Operation Timing 2
A
9
System clock period
Figure 21.13 Block Diagram of Noise Canceler
Sampling clock
D
Bit 7
1
Latch
C
Bit 6
Data 1
2
Q
Bit 5
3
D
Bit 4
Sampling
4
clock
Latch
C
Bit 3
5
[3] Set ACKBT
Q
Bit 2
Rev. 2.00 Sep. 24, 2008 Page 1059 of 1468
6
Bit 1
7
Section 21 I
Compare
detection
match
circuit
[3] Read ICDRR
Bit 0
8
A
2
C Bus Interface 2 (IIC2)
Internal SCL
internal SDA
REJ09B0412-0200
9
or
[4] Read ICDRR
Data 1
Data 2
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